B.Tech. CSE
B.Tech. CSE 3rd Sem
System Analysis and Design
Object Oriented Programming with C++
Mathematics - III
DIGITAL LOGIC AND DESIGN
Electronics Devices And Circuits
B.Tech. CSE 4th Sem
Data Structure with Algorithm
Computer System Architecture
Discrete Structure & Fuzzy Techniques
System Software
Data Communication & Networks
B.Tech. CSE 5th Sem
Operating System
Microprocessor And Interfaces
Computer Oriental Numerical Method
Formal Language & Automata Theory
Parallel Computing
B.Tech. CSE 6th Sem
RDBMS
Software Engineering
Analysis & Design of Algorithm
Advance Programming Through Java
Computer Graphics
B.Tech. CSE 7th Sem
Web Technology
Compiler Design
Network Security
Elective-I
Professional Elective-I
B.Tech. CSE 8th Sem
Artificial Intelligence and Expert Systems
Data Mining & Data Warehousing
GUI Programming (Using Vb.net)
Professional Elective-II

Guru Ghasidas Vishwavidyalaya
Bilaspur Bilaspur Chhattisgarhhttp://www.ggu.ac.in
B.Tech. CSE 3rd Sem
Subject: DIGITAL LOGIC AND DESIGN

UNIT - 1 BINARY SYSTEM

Binary Number, Number Base conversion, Octal and Hexadecimal Numbers Complements, Binary Codes Binary Storage and Registers, Binary Logic, Integrated Circuits
BOOLEANAL GBRA AND LOGIC GATES:
Basic Definitions Axiomatic, Definition of Boolean algebra, Basic Theorems and Properties of Boolean algebra, Boolean Functions Canonical and Standard Forms, Other Logic Operations, Digital Logic Gates, IC Digital Logic Families. NAND, NOR, EOR gates.


UNIT - 2 BOOLEAN FUNCTIONS COMBINATION LOIGC

The map method Two and Three Variable Maps, Four Variable Map, Product of sums Simplification, NAND and NOR implementation, Don’t Care Conditions, The Tabulation Method Combinational Logic, Design procedure Adders, Subtractors, Code Conversion, Analysis Equivalence Functions.


UNIT - 3 COMBINATIONAL LOGIC WITH MSI AND LSI

Introduction Binary Parallel Adder, Decimal, Adder, Magnitude Comparator, Decoders, Multiplexers, Read Only Memory (ROM), Programmable Logic Array (PLA).


UNIT - 4 SEQUENTIAL LOGIC

Introduction, Flip – Flops, triggering of Flips – Flops, Analysis of Clocked Sequential Circuits, State Reduction and Assignment. Flip – Flop Excitation Tables Design Procedure. Design of Counters, Design with State Equations.


UNIT - 5 REGISTERS, COUNTERS, MEMORY UNIT & FPGA PROGRAMING

Introduction, Registers, Shift Register, Ripple Counters, Synchronous Counters. Timing Sequences, The Memory Unit Examples of Random Access Memories, FPGA: Introduction, FPGA Programming.


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